`timescale  1 ns/1 ps

module top_tb();

`include "./spi_bfm.svh"
`include "./spi_drive.svh"

spi_bfm spi_bfm_i();

spi_drive  spi_drive_h;

logic                       clk = 0;
logic                       rst = 0;
always
    #(1s/100_000_000/2) clk = ~clk;

initial
begin
    #0us rst = 0;
    #2us rst = 1;
    #2us rst = 0;
end


parameter               SPI_MODE = 8'h03;
initial
begin
    force top_tb.spi_slave_coreEx01.spi_slave_recv_coreEx01.config_reg = SPI_MODE;
    spi_drive_h = new(spi_bfm_i);
    assert(spi_drive_h.randomize());
    // user code
    spi_drive_h.config_mode(SPI_MODE, 10_000_000);

    #10us spi_bfm_i.scs = 0;
    #1us spi_drive_h.send_byte(8'h55);
    #5us spi_drive_h.send_byte(8'haa);
    #5us spi_drive_h.send_byte(8'h33);
    #5us spi_drive_h.send_byte(8'h44);
    #5us spi_drive_h.send_byte(8'h77);
    #5us spi_drive_h.send_byte(8'h88);
    #5us spi_bfm_i.scs = 1;

    //#5us spi_drive_h.config_mode(8'h01, 20_000_000);
    //#5us spi_drive_h.send_byte(8'haa);

    //#5us spi_drive_h.config_mode(8'h02, 15_000_000);
    //#5us spi_drive_h.send_byte(8'haa);

    //#5us spi_drive_h.config_mode(8'h03, 15_000_000);
    //#5us spi_drive_h.send_byte(8'h55);
end

//logic                       s_axi_tvalid;
//logic   [07:00]             s_axi_tdata;
//initial
//begin
    //s_axi_tvalid = 0;
    //s_axi_tdata = 0;
    //#6us; s_axi_tvalid = 1; s_axi_tdata = 8'h88; #10ns; s_axi_tvalid = 0;
    //#10us; s_axi_tvalid = 1; s_axi_tdata = 8'hcd; #10ns; s_axi_tvalid = 0;
//end

initial
begin
    #4.5us spi_drive_h.read_byte();
    #5us spi_drive_h.read_byte();
end

spi_slave_core  #
(
        .DATA_W(       8               )
)

spi_slave_coreEx01
(
        .clk            (       clk             ),
        .rst            (       rst             ),
        .m_axi_tready   (                       ),
        .m_axi_tvalid   (                       ),
        .m_axi_tdata    (                       ),
        .s_axi_tready   (                       ),
        .s_axi_tvalid   (                       ),
        .s_axi_tdata    (                       ),
        .config_reg     (       SPI_MODE        ),
        .sclk           (       spi_bfm_i.sclk          ),
        .scs            (       spi_bfm_i.scs           ),
        .mosi           (       spi_bfm_i.mosi          ),
        .miso           (       spi_bfm_i.miso          )
) ;
endmodule
